Interpretation of Xilinx's 7 Series 28nm FPGA Packaging Strategy

You must be familiar with the story of buying a pearl and returning it. If the most valuable and technical silicon chip inside the chip is compared to a pearl, the package outside the chip, including pins, can be compared to a pearl.

Chip makers are all proud of being able to design the Pearl on the crown. If someone says they are engaged in packaging, they will most likely be regarded as the non mainstream of the chip industry.

However, a man named Gordon Moore came up with a Moore's law and clearly proposed that the price of the same pearl should be halved every 18 months. (this article was originally written by Kevin of openhw.org. Please indicate if you reprint it.). The source of chips, in the final analysis, is inexhaustible sand, while packaging and pins consume copper, gold, rare metals and other resources. Therefore, the speed at which the cost of packaging is reduced is much less than that of Moore's law. In this way, if the price of pearl remains unchanged, the price of pearl will one day be cheaper than that of pearl. There is no way. No matter how expensive the price is, it will be very cheap except n times.

Packaging is also expensive and cheap. The more pins, the more expensive, the higher the heat dissipation requirements. Therefore, if you want to achieve cheap packaging and low power consumption, it is the basic requirement.

When Xilinx began to develop Spartan, a low price series chip, in 1998, it was a multi pronged approach to reduce costs. Based on virtex series chips, it achieved low costs by reducing the complexity of silicon chips, controlling capacity, number of pins, power consumption, packaging form, etc. In 1998, the cost of silicon chip dominated the cost of the whole chip. Therefore, Xilinx made great efforts to design a new and simplified internal structure of silicon chip, reduce the complexity of silicon chip and reduce the size of die, which can greatly reduce the cost of the whole chip, and achieved a legend of Spartan, a low-cost FPGA series for more than 10 years.

By 2010, when Xilinx 7 series was released, the process node had reached 28nm. At this time, for a small capacity FPGA, the cost of die has been equal to or even lower than the cost of packaging. At this time, it is obviously not cost-effective to spend so much energy on chip design specifically to reduce the cost. It is better to use the same structure to reduce power consumption, and then use lower cost packaging to obtain the overall low cost of the chip.

Under this idea, Xilinx's 7 series, unified architecture FPGA was born. Although the names have become three, artix-7, kinex-7 and virtex-7, the internal structure, clock, speed and so on are all based on one architecture, that is, the asmbl technology architecture based on virtex series. The difference is only the combination of internal functions to serve different markets.

Due to the application of HKMG process, the power consumption is greatly reduced. In this way, as the cheapest device in the 7 series, artix-7 series can boldly adopt low-cost small packaging by taking advantage of low power consumption. In this way, it can make both rice and beads much cheaper, so as to achieve ultra-low price and impact the broader ASIC and ASIP market.

The kinex-7, because it does not contain the most expensive transceiver, has achieved high performance and low price in the application of the current mainstream 10g serial transceiver.

Of course, virtex-7 continues the noble blood of the traditional virtex series and continues to dominate the high-end market with the highest speed and density in the industry.

Although Moore's law continues as usual, quantitative change causes qualitative change, and many thinking modes in the industry need to be changed. When Moore's law finally ends, perhaps the most active field in the industry is packaging. In fact, at present, various stacking and packaging technologies are widely used in mobile phones, which is one of the signs of this trend.

Just like Xilinx invented FPGA and fabless business model, Xilinx's unified architecture once again did the right thing at the right historical turning point.

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